1. Field of the Invention
The present invention relates to a semiconductor circuit device for delaying received information by a constant time period to supply the delayed information, the time delay being variable.
2. Description of the Prior Art
In a digital image processing system such as a digital television unit and a digital video tape recorder, a delay element and a memory element (for example, a video RAM) are used to delay video signal by 1 H period (a horizontal scanning period), 2H period, or 1 frame period. In addition, a frame synchronization bit included in communication information must be detected to provide synchronization of communication in a communication terminal. In a frame synchronization detecting block in such a communication system, the delay element is used to detect a synchronization pattern. Large capacity and variability in a delay time from the point of view of a general purpose are required for the delay clement in such a field.
FIG. 1A is a diagram showing an example of a structure of a conventional variable length shift register capable of varying the delay time, which is disclosed in, for example, "MSM6901AS Variable Length Shift Register", Oki Electric Industry Co., Ltd., Technical News, S83-07.
The variable length shift register comprises variable length shift registers 7-1 to 7-n receiving n bit inputs DI-1 to DI-n, respectively, for delaying the same by a predetermined time period in response to bit length selection signals A1 to Ai, and output buffers 8-1 to 8-n receiving outputs of the variable length shift registers 7-1 to 7-n, respectively, for outputting delayed output data DO-1 to DO-n. The variable length shift registers 7-1 to 7-n have the same structure, so that the delay time is set by a combination of the bit length selection signals A1 to Ai. In the above described structure, the n bit input data DI-1 to DI-n are delayed in parallel by a predetermined time period, so that the n bit parallel delayed output data DO-1 to DO-n are obtained. More specifically, the respective variable length shift registers 7-1 to 7-n constitute a shift register of the number of stages of unit shift registers corresponding to a value set by the bit length selection signals A1 to Ai, so that input data are delayed by a predetermined time period.
FIG. 1B is a waveform diagram showing operation of the variable length shift register shown in FIG. 1A, that is, showing operation when the delay time is set to be five clock signals. Referring now to FIGS. 1A and 1B, description is made on operation of a conventional variable length shift register.
The delay time of each of the shift registers 7-1 to 7-n is set to be five clocks by the bit length selection signals A1 to Ai. The input data DI-k (k=1 to n) are written into the variable length shift registers 7-1 to 7-n in response to the rise of a clock signal CLK. On the other hand, the output data DO-k (k=1 to n) are outputted from each of the variable length shift registers 7-1 to 7-n in response to the rise of the clock signal CLK. However, since the output data are unwanted output data until a time period of five clock signals elapses since the input data DI-k were inputted, the output data during the time period of five clocks are made invalid. Then, the input data DI-k are sequentially outputted in response to the sixth clock and the subsequent clocks as valid output data DO-k. At that time, the delay time of five clocks exists between the input data DI-k and the output data DO-k.
The above described conventional variable length shift register changes the number of stages of unit shift registers in response to the bit length selection signals. Thus, a lot of unit shift registers serving as information storing means must be used to accommodate various delay times. This causes increase in the area required for the variable length shift register. However, storage capacity is small in spite of the area. Furthermore, power dissipation is large.
FIG. 2A is a diagram showing another structure of the conventional variable length shift register, which is disclosed in Japanese Patent Laying-Open Gazette No. 42634/1978. The variable length shift register of the prior art comprises a ring counter and a memory. A random access memory is used as the memory. Referring now to FIG. 2A, description is made of a structure of a conventional variable length shift register.
A subtracter 133 subtracts a "1" signal 106 from a signal 102 having a designated shift amount M applied from an external apparatus (not shown) and outputs an (M-1) signal 105. A comparator 134 compares the (M-1) signal 105 applied from the subtracter 133 with an address signal 104 applied from a counter 132, and outputs a load signal 203 when both coincide with each other. The counter 132 counts up a clock signal applied from the external apparatus. When the content of the counter 132 becomes (M-1), the counter 132 is reset to be 0 in response to a next-coming clock signal 300 when the load signal 203 from the comparator 134 and a "0" signal 107 are applied. More specifically, the counter 132 outputs M kinds of address signals 104 such as 0 to (M-1) with a cycle of M clocks. The memory 130 outputs as a read signal the content of an address designated by the address signal 104 in response to a timing signal CE (chip enable signal) 200 which enables reading/writing of the memory 130 from the external apparatus, and writes an input data signal 100 applied from the external apparatus into a location corresponding to an address designated by the address signal 104 in response to the CE signal 200 applied from the external apparatus and a timing signal WE (write enable signal) 201 which designates writing of the input data signal 100 into the memory 130. A register 131 latches a read signal 103 applied from the memory 130 in response to a data set signal 202 applied from the external apparatus and outputs an output data signal 101 to the external apparatus.
FIG. 2B is a waveform diagram showing operation of the variable length shift register shown in FIG. 2A. Referring now to FIGS. 2A and 2B, description is made on operation of the conventional variable length shift register using memory.
The address signal 104 circulates between 0 and (M-1) by the clock signal 300 and the load signal 203. Since the input data signal 100 is "1" and the address signal 104 is "0" at the first time 1 in a cycle P, "1" is written into an address 0 in the memory 130 in response to the CE signal 200 and the WE signal 201. In the same manner, at the second time 2, "0" is written into an address 1 in the memory 130. The same operation process is repeated until input data is written to an address (M-1) in the memory 130. The content of the address 0 in the memory 130, that is, "1" written at the first time 1 in the cycle P is outputted as the read signal 103 in response to the CE signal 200 represented by "R" at the first time 1 in the next cycle (P+1) (that is, after a time period of M clocks elapses from the first time 1 in the cycle P), because the address signal 104 is "0", and is latched to the register 131 in response to the data set signal 202, so that the output data signal 101 is obtained. On the other hand, the input data signal 100 of "0" is written into the address 0 in the memory 130 in response to the CE signal represented by "W" in FIG. 2B and the WE signal 201. In the same manner, the content of the address 1 in the memory 130 is read out in response to the CE signal 200 represented by "R" at the second time 2 in the cycle (P+1), because the address signal 104 is "1", so that "0" is outputted as the output data signal 101 by the register 131. On the other hand, the input data signal 100 of "1" is written into the address 1 in the memory 130 in response to the CE signal 200 represented by "W" and the WE signal 201. More specifically, at each time, in the memory 130, data is read out from an address designated by the address signal 104 in response to the CE signal 200 represented by "R" and then, the input data signal 100 is written into the address in response to the CE signal 200 represented by "W" and the WE signal 201. In the above described structure, the counter 132, the subtracter 133 and the comparator 134 constitute a ring counter having the values of 0 to (M-1) utilizing the designated shift amount M as a parameter.
In order to periodically generate an address of a memory, the variable length shift register of the prior art requires a subtracter for subtracting the shift amount M from the numerical value "1", a counter for counting up a clock and generating the address, and a comparator for detecting a coincidence of the subtracter output and the counter output to reset the counter, so that the number of circuits are large and the area of the variable length shift register can not be reduced. In addition, in the above described structure, an address is generated by the counter, and the memory requires a decoder for decoding the output of the counter, so that much time is required to input and output data due to a time loss in address generation and address decoding, and the operating speed is slow.
A variable length shift register using memory is disclosed in Japanese Patent Laying-Open Gazettes No. 38989/1978 and No. 42529/1978.
Japanese Patent Laying-Open Gazette No. 38989/1978 discloses a variable length shift register comprising a register for storing a shift amount M, an address counter for generating an address of a memory, a subtracter for subtracting an output of the register from an output of the address counter, a multiplexer for performing switching between the output of the subtracter and the output of the address counter, and a flip-flop for controlling reading/writing. In this structure, when data is written into an address (N+1), data at an address (N +1-M) is read out. Therefore, a delay amount M is obtained. However, according to the prior art, a circuit structure and a timing of controlling a signal are complicated, and the area can not so reduced. In addition, since the reading/writing is switched by inversion of an output of the flip-flop, high speed operation can not be performed.
Japanese Patent Laying-Open Gazette No. 42529/1978 discloses a variable length shift register comprising a random access memory, a variable N-ary counter for counting a clock which is synchronized with input data to generate an address of the random access memory, and a circuit for generating a timing signal of writing/reading in synchronization with the clock.
According to the prior art, a RAM (random access memory) is used as a memory element. However, since the RAM comprises not only a memory cell array but also a peripheral circuitry such as an address decoder and an input/output buffer, the RAM prevents the area from being reduced. In addition, since an output of the counter is applied to the RAM as an address signal to be decoded by the decoder in the RAM so as for a memory cell to be accessed, the operation speed can not be decreased.